Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Achuta Thippana"'
Autor:
Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, CJ Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, YS Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, SA Hwang
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Jason Tsai, Manzur Rahman, Lee-Kee Yong, Rolf Lagerquist, Henry Hsieh, Vincent Lin, Sa Huang, Sudhakar Maruthi, Elly Chiang, Wade Wu, Ericbill Wang, Hsinchen Chen, Ashish Nayak, Anand Rajagopalan, Tao Chen, Gordon Gammie, Curtis Lin, Cheng-Yuh Wu, Hugh Mair, Ramu Madhavaram, Gokulakrishnan Manoharan, Amjad Sikiligiri, Daniel Dia, Efron Ho, Jenny Wiedemeier, Barry Chen, Achuta Thippana, Madhur Jagota, Chi-Jui Chung, Po-Yang Hsu
Publikováno v:
ISSCC
This paper describes a new CPU subsystem featured in a 5G mobile SoC. The High-Performance (HP) core achieves a 3GHz clock frequency with full production yield across the fabrication range and operating environment. In contrast to previously publishe
Autor:
Rolf Lagerquist, Blundt Li, Ericbill Wang, Jenny Wiedemeier, Hsinchen Chen, Rory Huang, Lee-Kee Yong, Manzur Rahman, Vincent Lin, Sa Huang, Ashish Nayak, Achuta Thippana, Hugh Mair, Loda Chou, Michael Yanq, Ramu Madhavaram, Osric Su, Gordon Gammie, Alex Chiou
Publikováno v:
ISSCC
This paper introduces the heterogenous CPU complex of a fully integrated 5G mobile Smartphone SoC, implemented in 7nm FinFET technology. Circuit techniques developed to achieve competitive CPU PPA are detailed, and associated silicon results are pres
Autor:
Ray Tzeng, Cheng-Yuh Wu, Taner Dosluoglu, Chi-Hsueh Wang, Jin Son, David Yen, Hugh Mair, Girishankar Gurumurthy, Yi-Chang Zhuang, Wuan Kuo, Yuwen Tsai, Hung-Wei Wang, Ue Fu, Rolf Lagerquist, Kent Li, Achuta Thippana, Sumanth Gururajarao, Tony Hsieh, Ping Kao, Alice Wang, Mark Shane Peng, Gordon Lin, Jengding Wu, Anatoly Gelman, Daniel Dia, Lin Wen-Yi, Uming Ko, Gordon Gammie, Manzur Rahman, Ericbill Wang
Publikováno v:
ISSCC
This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains thre
Autor:
Amit Jain, Gordon Gammie, Jengding Wu, Hugh Mair, Shichin Ouyang, Leo Shieh, Minh Chau, Vincent Lin, Lee-Kee Yong, Achuta Thippana, Wuan Kuo, Ue Fu, Anirban Saha, Anshul Varma, Hsinchen Chen, Clavin Peng, Anand Rajagopalan, Ping Kao, Huajun Wen, Alfred Tsai, Brian Flachs, Syed Rahman, Rolf Lagerquist, Ericbill Wang, Uming Ko, Alice Wang, Mark Shane Peng, Chi-Jui Chung, Sumanth Gururajarao
Publikováno v:
ISSCC
This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS