Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Abraham Arceo de la Pena"'
Autor:
Stefan Schoeche, Daniel Schmidt, Marjorie Cheng, Aron Cepler, Abraham Arceo de la Pena, Jennifer S. Oakley
Publikováno v:
Metrology, Inspection, and Process Control XXXVII.
Autor:
Daniel Schmidt, Igor Turovets, Veeraraghavan S. Basker, Andrew M. Greene, Frougier Julien, Mary Breton, Aron Cepler, Marjorie Cheng, Dexin Kong, Nicolas Loubet, Mark Klare, Roy Koret, Jingyun Zhang, Abraham Arceo de la Pena, Ishtiaq Ahsan
Publikováno v:
2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with
Autor:
Tsuyoshi Furukawa, Anuja De Silva, Luciana Meli, Jing Guo, Dominik Metzler, Indira Seshadri, Ramakrishnan Ayothi, Yann Mignot, Nelson Felix, Dan Corliss, Abraham Arceo de la Pena, Lovejeet Singh, Yongan Xu
Publikováno v:
Advances in Patterning Materials and Processes XXXV.
Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask
Autor:
Robinhsinkuo Chao, Matthew Sendelbach, Susan Ng-Emans, Veeraraghavan S. Basker, Wei Ti Lee, Juntao Li, Gilad Barak, John G. Gaudiello, Brock Mendoza, Tenko Yamashita, Gangadhara Raja Muthinti, Abraham Arceo de la Pena, Aron Cepler, Nicolas Loubet, Dexin Kong
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
Multi-channel gate all around (GAA) semiconductor devices require measurements of more target parameters than FinFET devices, due in part to the increased complexity of the different structures needed to fabricate nanosheet devices. In some cases, mu
Autor:
Michael Shifrin, Robin Chao, Gangadhara Raja Muthinti, Matthew Sendelbach, Wei Ti Lee, Abraham Arceo de la Pena, Ronen Urenski, Susan Emans, Jacques Simon, John G. Gaudiello, Mary Breton, Aron Cepler, Yoav Etzioni
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXI.
Electrical test measurement in the back-end of line (BEOL) is crucial for wafer and die sorting as well as comparing intended process splits. Any in-line, nondestructive technique in the process flow to accurately predict these measurements can signi
Autor:
Tenko Yamashita, Shay Wolfling, Sivananda K. Kanakasabapathy, Gangadhara Raja Muthinti, Wei Ti Lee, Abraham Arceo de la Pena, Michael A. Guillorn, Juntao Li, Daniel Kandel, John G. Gaudiello, Susan Emans, K. Matney, Avron Ger, Matthew Wormington, Roy Koret, Aron Cepler, Matthew Sendelbach, Nicolas Loubet, Peter Gin, Robin Chao
Publikováno v:
SPIE Proceedings.
Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerge
Autor:
Peter Gin, Matthew Sendelbach, Robin Chao, Cornel Bozdog, Matthew Wormington, Tom Cardinal, Fee li Le, Brock Mendoza, Stuart A. Sieg, Raja Muthinti, John G. Gaudiello, Florence Nelson, Aron Cepler, Sivananda K. Kanakasabapathy, Shay Wolfling, B. Lherron, Mary Breton, Eric R. Miller, Abraham Arceo de la Pena, James J. Demarest, Nelson Felix
Publikováno v:
SPIE Proceedings.
Self-Aligned Quadruple Patterning (SAQP) is a promising technique extending the 193-nm lithography to manufacture structures that are 20nm half pitch or smaller. This process adopts multiple sidewall spacer image transfers to split a rather relaxed d
Autor:
Nicolas J Loubet, Juntao Li, Robin Chao, Chunwing Yeung, Julien Frougier, Curtis Durfee, Abraham Arceo de la Pena, Raja Muthinti, Zhenxing Bi, Muthumanickam Sankarapandian, Wenyu Xu, Yann Mignot, Stuart Sieg, Richard Conti, Basker Veeraraghavan, Hemanth Jagannathan, Bala Haran, Rama Divakaruni, Huiming Bu
Publikováno v:
ECS Meeting Abstracts. :1075-1075
Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels, a specific SiGe/Si superlattice epitaxy is employed, with SiGe being used a