Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Abhiram Prabhakar"'
Publikováno v:
IEEE Transactions on Communications. 50:1389-1396
We consider maximal-length linear congruential sequences generated using a simple recursion to generate the bipartite graph of a low-density parity-check (LDPC) code. The main advantage is that the graph structure of the codes (edge connections) can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d0155b291bce149426f78e98e8da098
https://doi.org/10.1109/tcomm.2002.802537
https://doi.org/10.1109/tcomm.2002.802537
Publikováno v:
2007 7th International Conference on ASIC.
This paper presents a design of VLSI architecture for the FEC (Forward Error Correction) decoding system supporting the Chinese National Terrestrial Digital TV Broadcasting Standard (GB20600-2006). The architecture of the FEC decoder includes a time-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5fa74aaf96417fed04fdf37a44be529
https://doi.org/10.1109/icasic.2007.4415783
https://doi.org/10.1109/icasic.2007.4415783
Publikováno v:
ICASSP (5)
We present a memory efficient serial low density parity check (LDPC) decoder that implements a modified sum product algorithm (SPA). The modification is similar to the approximate min constraint presented by C. Jones et al. (see IEEE Conf. Military C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00396affbc058d5c237bdbc340c45ae4
https://doi.org/10.1109/icassp.2005.1416235
https://doi.org/10.1109/icassp.2005.1416235
Publikováno v:
ICC
Maximal length linear congruential sequence (MLLCS) based LDPC codes have the advantage that the LDPC code graph can be generated at the receiver without having to explicity store the graph. Hence, these codes are advantageous when the same hardware
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2de9cb4ff1b31bdadbe1417227817b2d
https://doi.org/10.1109/icc.2005.1494672
https://doi.org/10.1109/icc.2005.1494672
Publikováno v:
ISCAS (2)
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this thr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41c771aac5eea82a89e91c1d76d09643
https://doi.org/10.1109/iscas.2003.1205887
https://doi.org/10.1109/iscas.2003.1205887