Zobrazeno 1 - 10
of 186
pro vyhledávání: '"Abdelkarim Mercha"'
Autor:
E. Dupuy, Geert Mannaert, Ben Kaczer, Jacopo Franco, Vincent De Heyn, Narendra Parihar, Anne Vandooren, Gaspard Hiblot, Sylvain Baudot, Abdelkarim Mercha
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 21:192-198
This work reports on charging damage induced by gate antennae in high- $\kappa $ (HK) Replacement Metal Gate (RMG) technology for the HK-first and HK-last integration flows, comparing plate and comb layouts. For the HK-first devices, a significant de
Autor:
Narendra Parihar, Goutham Arutchelvan, Jacopo Franco, Sylvain Baudot, Ann Opedebeeck, Steven Demuynck, Hiroaki Arimura, Lars-Ake Ragnarsson, Jerome Mitard, Vincent De Heyn, Abdelkarim Mercha
Publikováno v:
2021 IEEE International Integrated Reliability Workshop (IIRW).
Autor:
Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Trong Huynh-Bao, Julien Ryckaert, Aaron Thean, Piet Wambacq
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1669-1680
In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically anal
Autor:
Victor-H. Vega-Gonzalez, Ivan Ciofi, Praveen Raghavan, Dan Mocuta, Christopher J. Wilson, Rogier Baert, Antonino Contino, Philippe Roussel, Guido Groeseneken, Abdelkarim Mercha, Aaron Thean, Mustafa Badaroglu, Kristof Croes, Diederik Verkest
Publikováno v:
IEEE Transactions on Electron Devices. 63:2488-2496
We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu da
Publikováno v:
IEEE Transactions on Electron Devices. 62:1716-1724
For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants o
Autor:
Aaron Thean, Geert Eneman, Anabela Veloso, Kristin De Meyer, Praveen Raghavan, P. Schuddinck, Trong Huynh Bao, Diederik Verkest, Abdelkarim Mercha, D. Yakimets, Nadine Collaert, Marie Garcia Bardon
Publikováno v:
IEEE Transactions on Electron Devices. 62:1433-1439
In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices
Autor:
Nadine Collaert, Abdelkarim Mercha, C. Claey, A Benfdila, R Carin, Jean-Marc Routoure, H. Achour, Rachida Talmat, Bogdan Cretu, Eddy Simoen
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2013, 90, pp.160-165. ⟨10.1016/j.sse.2013.06.006⟩
Solid-State Electronics, Elsevier, 2013, 90, pp.160-165. ⟨10.1016/j.sse.2013.06.006⟩
International audience; In this paper, DC and noise measurements on strained and unstrained SOI p-FinFETs were performed at cryogenic temperatures (10 K) in order to evaluate the device performances and study the low frequency noise mechanisms. The m
Autor:
Eddy Simoen, C. Claeys, Abdelkarim Mercha, Daisuke Kobayashi, Felice Crupi, Serana Iacovo, Alessio Griffoni, Philippe Roussel
Publikováno v:
ECS Transactions. 50:213-222
Although scaled down technologies may suffer from statistical parameter fluctuations caused by process variability, they are potentially radiation hard from a total-dose perspective. Therefore, the proton radiation hardness of a high-κ/metal gate 45
Autor:
Piet Wambacq, Julien Ryckaert, Aaron Thean, Sushil Sakhare, Abdelkarim Mercha, Trong Huynh-Bao, Diederik Verkest
Publikováno v:
SPIE Proceedings.
In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32
Autor:
Aaron Thean, Diederik Verkest, Abdelkarim Mercha, Julien Ryckaert, Piet Wambacq, Trong Huynh-Bao, Sushil Sakhare, D. Yakimets
In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3132db2cbe43cf249b92f32752bc12e4
https://doi.org/10.1109/ted.2015.2504729
https://doi.org/10.1109/ted.2015.2504729