Zobrazeno 1 - 6
of 6
pro vyhledávání: '"AL KHAYAT , Rachid"'
Autor:
AL KHAYAT, Rachid
Les systèmes sur puces dans le domaine des communications numériques deviennent extrêmement diversifiés et complexes avec la constante émergence de nouveaux standards et de nouvelles applications. Dans ce domaine, le turbo-décodeur est l'un des
Externí odkaz:
http://tel.archives-ouvertes.fr/tel-00821906
http://tel.archives-ouvertes.fr/docs/00/82/19/06/PDF/2012telb0247_Al_Khayat_Rachid.pdf
http://tel.archives-ouvertes.fr/docs/00/82/19/06/PDF/2012telb0247_Al_Khayat_Rachid.pdf
Autor:
Al Khayat, Rachid
Publikováno v:
Electronics. Télécom Bretagne, Université de Bretagne-Sud, 2012. English
Systems-on-chips in the field of digital communications are becoming extremely diversified and complex with the continuous emerging of new digital communication systems and standards. In this field, Turbo decoding is one of the most computation, comm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::2413ef4d283524ec95d63404cdbce8fd
https://tel.archives-ouvertes.fr/tel-00821906/document
https://tel.archives-ouvertes.fr/tel-00821906/document
Autor:
MURUGAPPA VELAYUTHAN , Purushotham, Reddy , Pallavi, AL KHAYAT , Rachid, BAZIN , Jean-Noël, BAGHDADI , Amer, Clermidy , Fabien, Jezequel , Michel
Publikováno v:
SOC-SIP : colloque national du groupe de recherches System On Chip-System In Package
SOC-SIP : colloque national du groupe de recherches System On Chip-System In Package, Jun 2012, Paris, France. 2012
SOC-SIP : colloque national du groupe de recherches System On Chip-System In Package, Jun 2012, Paris, France
SOC-SIP : colloque national du groupe de recherches System On Chip-System In Package, Jun 2012, Paris, France. 2012
SOC-SIP : colloque national du groupe de recherches System On Chip-System In Package, Jun 2012, Paris, France
International audience; In order to meet flexibility and performance constraints of current and future digital communication applications, multiple ASIPs combined with dedicated communication and memory architectures are required. In this work we con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::333a0d051986ef7459cff0d01f4e2001
https://hal.archives-ouvertes.fr/hal-00725184/file/47_GDR_SOC_SIP_Flexible_Multi-ASIP_SoC_for_Turbo_LDPC_Decoder.pdf
https://hal.archives-ouvertes.fr/hal-00725184/file/47_GDR_SOC_SIP_Flexible_Multi-ASIP_SoC_for_Turbo_LDPC_Decoder.pdf
Publikováno v:
Proceedings SOC 2012 IEEE International Symposium on System-on-Chip
SOC 2012 IEEE International Symposium on System-on-Chip
SOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland
SOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland. 2012
SOC 2012 IEEE International Symposium on System-on-Chip
SOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland
SOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland. 2012
International audience; Architecture efficiency, in terms of performance/area, of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works on application-specific in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::f5367accbdc431cfa89bbc71adfdbba5
https://hal.archives-ouvertes.fr/hal-00797562
https://hal.archives-ouvertes.fr/hal-00797562
Publikováno v:
Colloque national du groupe de recherches System On Chip-System In Package (SOC-SIP)
Colloque national du groupe de recherches System On Chip-System In Package (SOC-SIP), Jun 2010, Paris, France
Colloque national du groupe de recherches System On Chip-System In Package (SOC-SIP), Jun 2010, Paris, France. 2010
Colloque national du groupe de recherches System On Chip-System In Package (SOC-SIP), Jun 2010, Paris, France
Colloque national du groupe de recherches System On Chip-System In Package (SOC-SIP), Jun 2010, Paris, France. 2010
International audience; In todays digital baseband implementation, energy efficiency, flexibility, high performance and low power are major requirements for channel decoding. In this paper we present a detailed power consumption analysis of a flexi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::0315a6ab0f293cb8fd7112c15d57172d
https://hal.science/hal-00632784
https://hal.science/hal-00632784
Publikováno v:
2012 International Symposium on System on Chip (SoC); 1/ 1/2012, p1-7, 7p
