Zobrazeno 1 - 10
of 29
pro vyhledávání: '"AHPL"'
Autor:
Zainalabedin Navabi
Publikováno v:
DTIS
The history of hardware description language goes back to 1960's when IBM introduced APL (A Programming Language) for their in-house digital circuit modeling and simulation. The early 1970's witnessed a rise of HDLs like AHPL (originally derived from
Autor:
Assim Sagahyroon
Publikováno v:
IEEE Transactions on Education. 43:449-454
As the size and complexity of digital systems increase, more CAD tools are introduced in the hardware design process; a recent addition to this process is the use of hardware description languages (HDLs). Historically, HDL-based design courses have b
Autor:
Kamalakar V Gajare, Sachin A Upasani, Vidyadhar G Vaidya, Vidyadhar S Kumbhar, Amol B Kamthe, Sanjay U Nipanikar
Publikováno v:
Ancient Science of Life
Ancient Science of Life, Vol 36, Iss 3, Pp 117-128 (2017)
Ancient Science of Life, Vol 36, Iss 3, Pp 117-128 (2017)
Objectives: The main objective of the present study was to assess efficacy and safety of AHPL/AYTOP/0113 cream, a polyherbal formulation in comparison with Framycetin sulphate cream in acute wounds. Methodology: It was an open label, randomized, comp
Autor:
Y. Chu, F.J. Hill, D.L. Dietmeyer, B. Johnson, G. Ordy, C.W. Rose, M. Roberts, J.R. Duley, M.R. Barbacci
Publikováno v:
IEEE Design & Test of Computers. 9:69-81
Current hardware description languages (HDLs) benefit from the efforts of designers of hardware description languages dating back to the mid 1960s. The developers of six HDLs discuss their motivations and their views of how their work relates to the
Publikováno v:
ICASSP
A data flow general purpose digital signal processor has been previously developed [1] for real time applications of digital signal processing. The Data Flow Signal Processor (DFSP) is attached to a host computer, and is based on a binary tree struct
Publikováno v:
Proceedings. Electrotechnical Conference Integrating Research, Industry and Education in Energy and Communication Engineering'.
A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a
Autor:
Zainalabedin Navabi
Publikováno v:
Proceedings., Eighth University/Government/Industry Microelectronics Symposium.
The author describes hardware description languages (HDLs) and various levels of abstraction. He then examines applications of these languages for teaching purposes. This is illustrated by use of examples in commonly used teaching HDLs. The VHSIC HDL
Autor:
Masud, Manzer, 1950
With the advent of LSI and VLSI technology, the demand and affordability of custom tailored design has increased considerably. A short turnaround time is desirable along with more credible testing techniques. For a low-production device it is necessa
Externí odkaz:
http://hdl.handle.net/10150/281995
Autor:
Navabi, Zainalabedin, 1952
Manual design methods used successfully up to now for SSI and MSI parts are inadequate for logically complex and densely packed VLSI circuitry. Automating the design process has, therefore, become an essential goal of present-day practice. Hardware d
Externí odkaz:
http://hdl.handle.net/10150/290569