Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Autor: F.O. Franca Rafael, N. da Silva Iseu, D. Petrović Zorica, Morbelli Silvia, Dong Pin, Haghparast-kenari Beheshteh, P. Petrović Vladimir, Daryani Ahmad, Taghi Rahimi Mohammad, Kishore Baireddy, N.L. de Morais Clarice, A.N. Azevedo Elisa, da Silva Santos Lucas, Marini Cecilia, Brahmeshwari Gavaji, Zhu Jing-Jing, de Pilla Varotti Fernando, Ran Hao, César Dias Lopes Julio, Sharif Mehdi, Simijonović Dušica, Pereira de Freitas Rossimiriam, I.O. de Sousa Larissa, C. Lima Morganna, Cui Yingtong, Yan Yong, Prasoona Gumpula, Nayeri Tooran, Sadhu Arindam, Dey Sarkar Rimpa, Fillipe Langanke de Carvalho Matheus, Claudia de Souza Pinto Ana, Pan Xin, Branković Jovica, Brondi Alves Rosemeire, Miceli Alberto, A. Bogdanović Goran, Sarvi Shahabeddin, Raffa Stefano, Wu Xue-Jun, M. Carvalho Bruno, Li Jing-Min, Li Xin-Qian, Sambuceti Gianmario, Jiang Ting-Ting, Wu Shu-Hui, Ahmadpour Ehsan, Quan Guilan, Liu Weibin, Luisa da Fonseca Amanda, Das Kunal, Bauckneht Matteo, Milovanović Vesna, Liu Yu-Ying, Ray Kanjilal Maitreyi, De Debashis, Cossu Vanessa, Novaković Slađana, Mladenović Milan, Chen Xiang, Wu Chuanbin, Isabella Donegani Maria, Huang Ying

Publikováno v: Micro and Nanosystems. 13:186-199

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurab

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::780bbe4554679d04816fecce8c58bc19
https://doi.org/10.2174/1876402912999200602171146