Zobrazeno 1 - 10
of 47
pro vyhledávání: '"A.K. Stamper"'
Autor:
Eric J. White, Russell T. Herrin, Christopher V. Jahnes, I. Vitomirov, Z.X. He, Dana Dereus, D. R. Miga, S. E. Luce, Shawn J. Cunningham, Art Morris, William J. Murphy, S. R. Dupuis, Jeffrey C. Maling, A. Gupta, A.K. Stamper
Publikováno v:
2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.
MEMS capacitor switches have been integrated with high voltage CMOS ICs. The MEMS were formed with the final three AlCu wiring levels in SiO 2 using a planar sacrificial silicon cavity process. The MEMS cavities were hermetically sealed at less than
Autor:
M. Gordon, S. St Onge, Edward J. Gordon, Hanyi Ding, Alvin J. Joseph, Matthew D. Moon, Mete Erturk, J. Dunn, A.K. Stamper, Z.X. He, Ebenezer E. Eshun, Douglas M. Daley, Douglas D. Coolbaugh
Publikováno v:
2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.
High quality factor inductors and highly matched low capacitance density horizontal parallel plate metal-insulator-metal capacitors were fabricated in 130nm RF-CMOS technology with minimal or zero processing step addition. The high quality factor ind
Autor:
Terry A. Spooner, Kaushik Chanda, Birendra N. Agarwala, Timothy J. Dalton, Jason Gill, Edward C. Cooney, C.-C. Yang, Daniel C. Edelstein, Clevenger Leigh Anne H, Andy Cowley, A. Simon, A.K. Stamper, Du Binh Nguyen
Publikováno v:
Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier
Autor:
Z. Karim, G. Bomberger, Stephan A. Cohen, Richard Wistrom, E. Adams, K. MacWilliams, M. Gibson, W. Zhu, Jeff Gambino, A. Gupta, A.K. Stamper, R. Bourque, M. Lavoie, J. Tian
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
A single pass-multistation deposition tool was used to deposit an IMD film which consisted of multiple FSG layers with optimized interfaces between the layers. The composite film had improved stability, F diffusion resistance, and electrical properti
Publikováno v:
Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
Electromigration in 0.23 /spl mu/m wide Cu dual-damascene lines connected to W underlayers has been investigated. Void growth at the vicinity of the cathode end of the line/via was determined to be the cause of the line failure. The distribution of f
Autor:
V. McGahay, B. Porth, T. Pricer, H. Wildman, C. Benson, C. Senowitz, M. Gibson, A. Piper, Edward C. Cooney, T. Standaert, R. Kontra, A.K. Stamper, Stephen E. Luce, J. Gambino, P. Biolsi, Tom McDevitt
Publikováno v:
Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).
The integration of Cu with low-k dielectrics poses a number of challenges. In this paper, we describe yield issues associated with integration of three different low-k dielectrics; FSG (fluorosilicate glass), OSG (organosilicate glass), and polymers.
Publikováno v:
1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).
The increase in ratio of wiring RC delay to the intrinsic transistor RC delay is motivating the IC industry to move from subtractive-aluminum to damascene-copper wiring. In addition to having 40% lower sheet resistance, damascene copper has significa
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
Measured and modeled back-end-of-the-line (BEOL) RC delay data are presented for multilevel sub-0.25 /spl mu/m generation CMOS ICs. The aluminum and copper BEOL levels were fabricated using metal RIE and damascene processing, respectively. Aluminum B
Autor:
A.K. Stamper, T. Katsetos, P. C. Andricacos, John E. Heidenreich, Stephen E. Luce, John Owen Dukovic, Ronald D. Goldblatt, Naftali E. Lustig, Richard A. Wachnik, J. Slattery, Daniel C. Edelstein, A. Simon, Thomas L. McDevitt, H. S. Rathore, Cyprian E. Uzoh, William J. Cote, P. McLaughlin
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 /spl mu/m CMOS products later this year. Features of this technology are presented here, as well as functional ver
Publikováno v:
IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).
Historically, the semiconductor industry has made chip speed the focus of its high performance CMOS logic development strategy. For the wires and insulators used in the back-end-of-the-line (BEOL), this has driven the industry to use damascene tungst