Zobrazeno 1 - 10
of 51
pro vyhledávání: '"A.A. Yasseen"'
Akademický článek
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Publikováno v:
Scopus-Elsevier
Publikováno v:
Journal of Microelectromechanical Systems. 8:172-179
This paper explores the use of thick glass films as suitable alternatives to CVD oxide films for use as sacrificial, planarization, and passivation layers in polysilicon surface micro-machining processes. Such glasses can be spin-coated to produce fi
Publikováno v:
Journal of Microelectromechanical Systems. 8:237-242
As an alternative to conventional SiC reactive ion etching (RIE), polycrystalline (poly-SiC) films were patterned into micron-sized structures using sacrificial SiO/sub 2/ and polycrystalline silicon (polysilicon) molds in conjunction with mechanical
Publikováno v:
IEEE Journal of Selected Topics in Quantum Electronics. 5:26-32
This paper describes a 1/spl times/8 rotary electrostatic micromotor optical switch fabricated using high-aspect-ratio micromachining technology to produce silicon or nickel components which are subsequently assembled to form a switch. The switch con
Publikováno v:
Journal of The Electrochemical Society. 146:327-330
In order to develop a low-cost alternative to diamond-based polishing slurries for SiC, mechanical polishing of 3C-SiC films using SiC-based slurries was studied, and an optimized polishing recipe was developed. The relationship among applied force,
Akademický článek
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Publikováno v:
Journal of Electronic Materials. 27:L17-L20
This paper reports on a process to fabricate single-crystal 3C-SiC on SiO2 structures using a wafer bonding technique. The process uses the bonding of two polished polysilicon surfaces as a means to transfer a heteroepitaxial 3C-SiC film grown on a S
Publikováno v:
Materials Science Forum. :223-226
Publikováno v:
Journal of The Electrochemical Society. 144:237-242
This paper explores the use of chemical-mechanical polishing (CMP) in polysilicon surface micromachining for removing the inherent surface roughness of polysilicon to create a mirror surface finish and for globally planarizing the wafer surface to ex