Zobrazeno 1 - 3
of 3
pro vyhledávání: '"A. R. Iga Jadue"'
Autor:
Katell Morin-Allory, T. Ferreira de Paiva Leite, M. Diallo, Laurent Fesquet, Sylvain Engels, Yoan Decoudu, O. Rolloff, A. R. Iga Jadue, R. Possamai Bastos
Publikováno v:
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019)
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru
VLSI-SoC
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2019), Oct 2019, Cuzco, Peru
VLSI-SoC
The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a473f5fb3f6a87d6ad5c075073684d27
https://hal.archives-ouvertes.fr/hal-02170157
https://hal.archives-ouvertes.fr/hal-02170157
Autor:
T. Ferreira de Paiva Leite, A. R. Iga Jadue, R. Possamai Bastos, Laurent Fesquet, O. Rolloff, M. Diallo
Publikováno v:
IEEE International Symposium on Circuits & Systems (ISCAS 2018)
IEEE International Symposium on Circuits & Systems (ISCAS 2018), May 2018, Florence, Italy
ISCAS
IEEE International Symposium on Circuits & Systems (ISCAS 2018), May 2018, Florence, Italy
ISCAS
Dynamically scaling down the voltage of integrated systems is an effective technique for enabling low-power operation modes. The system is partitioned into several subcircuits, and inactive parts are dynamically biased with low voltages. Additionally
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ae23ba889fd9e603427a1892cef1de26
https://hal.univ-grenoble-alpes.fr/hal-01726964
https://hal.univ-grenoble-alpes.fr/hal-01726964
Autor:
R. Possamai Bastos, Philippe Maurine, Jean-Max Dutertre, R. Iga Jadue, R.A. Camponogara Viera
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, Elsevier, 2017, 76-77, pp.68-74. ⟨10.1016/j.microrel.2017.07.007⟩
Microelectronics Reliability, Elsevier, 2017, 76-77, pp.68-74. ⟨10.1016/j.microrel.2017.07.007⟩
International audience; This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cf1b46a3ea83c23910a7406ff8cb2322
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01690185
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01690185