Zobrazeno 1 - 10
of 16
pro vyhledávání: '"A. A. Mikhteeva"'
Autor:
A. A. Mikhteeva, N. V. Kolesov
Publikováno v:
Naučno-tehničeskij Vestnik Informacionnyh Tehnologij, Mehaniki i Optiki, Vol 19, Iss 3, Pp 523-531 (2019)
Subject of Research. High-resolution successive approximation analog-to-digital converters include a digital-to-analog converter with multiple capacitor arrays and have significant nonlinearity. Existing methods for nonlinearity reducing are aimed p
Externí odkaz:
https://doaj.org/article/e524fc464a72471199578bdb7f777b62
Publikováno v:
Naučno-tehničeskij Vestnik Informacionnyh Tehnologij, Mehaniki i Optiki, Vol 18, Iss 3, Pp 479-486 (2018)
Subject of Research. The paper considers the research of verification methods for behavioral models by the field-programmed gate array (FPGA). Applying verification with FPGA gives the possibility to identify functional errors, which are not determin
Externí odkaz:
https://doaj.org/article/82f58993659f4dd2ab09c9c34d8588fd
Autor:
A. A. Mikhteeva, I. V. Lemko
Publikováno v:
Naučno-tehničeskij Vestnik Informacionnyh Tehnologij, Mehaniki i Optiki, Vol 18, Iss 2, Pp 331-338 (2018)
Subject of Research.Parasitic parameters, which appear on layout design stage of analog schematic model, cause negative effect on analog block performance. The presence of negative effect of parasitic parameters can be the reason for block inadequacy
Externí odkaz:
https://doaj.org/article/63c6c7c213054cd3b57b776cf819a167
Autor:
P.P. Khlyabich, I. A. Potapova, A.P. Bobrovsky, V.V. Kostsov, N. V. Dyachenko, Yu. B. Rzhonsnitskaya, N. A. Sanotskaya, E.Yu. Mikhteeva
Publikováno v:
Izvestiâ vysših učebnyh zavedenij. Priborostroenie. 64:384-391
Publikováno v:
Proceedings of the International Multidisciplinary Scientific GeoConference SGEM. 2018, Vol. 18, p1103-1110. 8p.
Autor:
Iliya V. Lemko, Anna A. Mikhteeva
Publikováno v:
Naučno-tehničeskij Vestnik Informacionnyh Tehnologij, Mehaniki i Optiki, Vol 18, Iss 2, Pp 331-338 (2018)
Subject of Research.Parasitic parameters, which appear on layout design stage of analog schematic model, cause negative effect on analog block performance. The presence of negative effect of parasitic parameters can be the reason for block inadequacy
Autor:
Jsc Concern Csri Elektropribor, I. V. Lemko, A. A. Mikhteeva, N. N. Nevirkovets, D. V. Kostygov, Ya. V. Belyaev
Publikováno v:
Problems of advanced micro- and nanoelectronic systems development. :49-56
Publikováno v:
Journal of Physics: Conference Series. 1536:012016
The digital integrated circuit is the main part of different sensors. It performs signal processing, controlling of a system and provides interface with external devices. Timing analysis is a basic verification method of digital integrated circuits.
Autor:
A. A. Mikhteeva, Yu. A. Andryakov, I. V. Lemko, Ya. V. Belyaev, N. N. Nevirkovets, D. V. Kostygov
Publikováno v:
2017 24th Saint Petersburg International Conference on Integrated Navigation Systems (ICINS).
Layout design stage of an integrated circuit for a micromechanical accelerometer is considered. A method for automated placement of repeating elements of analog blocks is proposed. The method takes into account area restrictions and placement of a bl
Publikováno v:
Journal of Structural Chemistry. 46:1082-1085
Images of cleaved surfaces were obtained for 53ZrF4-20BaF2-4LaF3-3AlF3-20NaF (ZBLAN) glasses and fused quartz using an NTMDT atomic force microscope. It is shown that the scatter of particle size depends on the cooling rate and is 21–48.5 A for the