Zobrazeno 1 - 4
of 4
pro vyhledávání: '"葉威志"'
Autor:
Yeh, Wei-Chih, 葉威志
105
Single Carrier Frequency Division Multiple Access (SC-FDMA), which has been selected as the uplink transmission technique of Long Term Evolution (LTE), is also called Discrete Fourier Transform-Spread Orthogonal Frequency Division Multiplexi
Single Carrier Frequency Division Multiple Access (SC-FDMA), which has been selected as the uplink transmission technique of Long Term Evolution (LTE), is also called Discrete Fourier Transform-Spread Orthogonal Frequency Division Multiplexi
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/8etu7g
Autor:
Wei-Jeih Yeh, 葉威志
98
In this paper, we propose a novel scheme in performing feature statistics normalization techniques for robust speech recognition. In the proposed approach, the processed temporal domain feature sequence is first converted into the modulation
In this paper, we propose a novel scheme in performing feature statistics normalization techniques for robust speech recognition. In the proposed approach, the processed temporal domain feature sequence is first converted into the modulation
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/44202171335895740151
Autor:
Wei-Chih Yeh, 葉威志
95
According to some researches, no matter in the time domain or in the spatial domain, that the usage of spectrum with utilization ranging from 15% to 85% in the bands below 3 GHz. At frequency above 3 GHz the actual utilization is dramatically
According to some researches, no matter in the time domain or in the spatial domain, that the usage of spectrum with utilization ranging from 15% to 85% in the bands below 3 GHz. At frequency above 3 GHz the actual utilization is dramatically
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/84758192239282289005
Autor:
Wei-Chih Yeh, 葉威志
92
In modern VLSI designs, the complexity of a chip critically increases and the numbers of wires and gates enormously grow. It becomes difficult to route wires and place buffers to meet timing in limited space. For example, the nets which are r
In modern VLSI designs, the complexity of a chip critically increases and the numbers of wires and gates enormously grow. It becomes difficult to route wires and place buffers to meet timing in limited space. For example, the nets which are r
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/53541676068168126606