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pro vyhledávání: '"白騏睿"'
Autor:
Qi-Rui Bai, 白騏睿
107
In the thesis, we propose an AES processor architecture, which can handle 128-bit data input each time by executing instructions. The 32-bit input is in the order of the data and then the external key. The external key can support the AES 12
In the thesis, we propose an AES processor architecture, which can handle 128-bit data input each time by executing instructions. The 32-bit input is in the order of the data and then the external key. The external key can support the AES 12
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/2635kr
