Zobrazeno 1 - 2
of 2
pro vyhledávání: '"周相攸"'
Autor:
Chou Hsiang Yu, 周相攸
89
We propose a timing-driven non-slicing floorplanner based on a modified force-directed method in this study. In deep sub-micron design, timing closure issue becomes more critical than chip area. We extract critical paths from gate-level desig
We propose a timing-driven non-slicing floorplanner based on a modified force-directed method in this study. In deep sub-micron design, timing closure issue becomes more critical than chip area. We extract critical paths from gate-level desig
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/58256965469330328957
