Zobrazeno 1 - 10
of 26
pro vyhledávání: '"тестовая система"'
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 77-84 (2019)
This article presents an approach to standalone verification of I/O Memory Management Unit with virtualization supporting. We presented the base architecture of the test system. The main problems encountered during the verification of IOMMU with virt
Externí odkaz:
https://doaj.org/article/233c0a2ccdf84ad49f08a6dfc0240aab
Autor:
Pavel Viktorovich Frolov
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 59-66 (2019)
Development of system-on-chips or network-on-chips requires verification of standalone units (peripherals and commutators) and a system as a whole. An approach to test development for verification of programmable standalone units is presented. The te
Externí odkaz:
https://doaj.org/article/c2d99cc14ffc43978bfeb8d1314318e1
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 67-76 (2019)
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and erro
Externí odkaz:
https://doaj.org/article/b41b9ad177b24aebb9b6de5ceb976d61
Publikováno v:
Труды Института системного программирования РАН, Vol 29, Iss 4, Pp 257-268 (2018)
This article proposes approaches used to verify 10 Gigabit Ethernet controllers developed by MCST. We present principles of the device operation - they provide a set of memory-mapped registers and use direct memory access, and their characteristics.
Externí odkaz:
https://doaj.org/article/8e8cc685a8c7448dbd8e3c26bbd6f703
Publikováno v:
Труды Института системного программирования РАН, Vol 28, Iss 3, Pp 161-172 (2018)
The paper presents an overview of approaches used in verifying correctness of multicore microprocessors caches. Common properties of memory subsystem devices and those specific to caches are described. We describe the method to support memory consist
Externí odkaz:
https://doaj.org/article/8cb468c606d64161ac2ec078e6183c72
Autor:
D. A. Lebedev, I. A. Stotland
Publikováno v:
Труды Института системного программирования РАН, Vol 30, Iss 3, Pp 183-194 (2018)
The paper proposes some approaches to functional verification of microprocessor communication controllers based on developing layered UVM (Universal Verification Methodology) test systems. In modern microprocessor systems there are a lots of controll
Externí odkaz:
https://doaj.org/article/f829b74cea6a4b15b4e6b16030d77670
Autor:
D.A. Lebedev, M.V. Petrochenkov
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 67-76 (2019)
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and erro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e652788064455e7bdc931d3e27ff0adc
https://ispranproceedings.elpub.ru/jour/article/view/1180
https://ispranproceedings.elpub.ru/jour/article/view/1180
Nowadays we need the ability to receive information from different sources, use it and create it independently. Practical use of information and communication technologies provide new teaching opportunities, greatly facilitate the work of teachers, i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2635::61355a730671be69634702fcc870d9f4
https://ela.kpi.ua/handle/123456789/41435
https://ela.kpi.ua/handle/123456789/41435
Publikováno v:
Освітологічний дискурс, Iss 1 (3) (2014)
Статья посвящена проблеме повышения точности педагогических измерений. Приведенные результаты позволяют уточнить методику использов
Externí odkaz:
https://doaj.org/article/73b829db47ae4bb5afef2c1a287ed25b
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 77-84 (2019)
This article presents an approach to standalone verification of I/O Memory Management Unit with virtualization supporting. We presented the base architecture of the test system. The main problems encountered during the verification of IOMMU with virt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fd1c84b0d2f9b0267d5ceff08f82b341
https://doi.org/10.15514/ispras-2019-31(3)-7
https://doi.org/10.15514/ispras-2019-31(3)-7