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Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 135-144 (2019)
Data access conflicts may arise in hardware designs. One of the ways of detecting such conflicts is static analysis of hardware descriptions in HDL. We propose a static analysis-based approach to data conflicts extraction from HDL descriptions. This
Externí odkaz:
https://doaj.org/article/3d0ddb77f1c34f1ea6abc700fbd9406f
Autor:
M. S. Lebedev, S. A. Smolov
Publikováno v:
Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is
Externí odkaz:
https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae
Autor:
S. A. Smolov, M. S. Lebedev
Publikováno v:
Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 135-144 (2019)
Data access conflicts may arise in hardware designs. One of the ways of detecting such conflicts is static analysis of hardware descriptions in HDL. We propose a static analysis-based approach to data conflicts extraction from HDL descriptions. This