Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Takahide Ikeda"'
Autor:
Kazuo Kanetani, Takahide Ikeda, Noriyuki Homma, Masami Usami, Kunihiko Yamaguchi, T. Masuda, Keiichi Higeta, T. Kikuchi, T. Kusunoki, Youji Idei, Masayuki Ohayashi, Kenichi Ohhata, Hiroaki Nambu
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:491-499
An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achievin
Autor:
Youji Idei, M. Odaka, Noriyuki Homma, Hiroaki Nambu, Kunihiko Yamaguchi, Toshiro Hiramoto, Kenichi Ohhata, Takahide Ikeda, Nobuo Tamba, Kazuo Kanetani, Yoshiaki Sakurai, K. Watanabe
Publikováno v:
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.
An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise;
Autor:
Kenichi Ohhata, Youji Idei, Nobuo Tamba, Kazuo Kanetani, Noriyuki Homma, M. Odaka, Toshiro Hiramoto, Takahide Ikeda, Hiroaki Nambu, Kunihiko Yamaguchi, Yoshiaki Sakurai, K. Watanabe
Publikováno v:
Proceedings of the 1991 Bipolar Circuits and Technology Meeting.
A redundancy technique suitable for ultra-high-speed SRAMs is developed using focused-ion-beam and laser-chemical-vapor-deposition. This technique is applied to a 64 Kb SRAM with a 1.5 ns access time without deterioration of the ultra-high-speed char
Publikováno v:
1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).
It has been noted that the soft error rate of the partially depleted SOI (PD-SOI) SRAM is not improved as compared with bulk CMOS SRAMs due to floating body effects through simulation (Tosaka et al. 1995). There has been no soft error data reported i
Autor:
K. Watanabe, E. Yoshida, Y. Tamaki, N. Tamba, H. Yamaguchi, Takayuki Hashimoto, S. Wada, Toshiyuki Kikuchi, Takahide Ikeda, Y. Onishi
Publikováno v:
Proceedings of International Electron Devices Meeting.
A 0.35 /spl mu/m ECL-CMOS technology has been developed to achieve high speed and high density LSIs for mainframe computers. A high speed bipolar transistor with cutoff frequency f/sub T/ of 30 GHz and a 30 /spl mu/m/sup 2/ 6T-CMOS memory cell with a
Autor:
Yoshiaki Sakurai, M. Odaka, Kunihiko Yamaguchi, K. Watanabe, Nobuo Tamba, Youji Idei, Kenichi Ohhata, Hiroaki Nambu, Takahide Ikeda, Kazuo Kanetani, Toshiro Hiramoto, Noriyuki Homma
Publikováno v:
1991 Symposium on VLSI Circuits.
Autor:
Suguru Tachibana, Hisayuki Higuchi, Masanori Odaka, Atsuo Watanabe, Takahide Ikeda, Suzuki Makoto
Publikováno v:
Extended Abstracts of the 1986 International Conference on Solid State Devices and Materials.