Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Hironori Kasahara"'
Publikováno v:
IEICE Transactions on Electronics. :85-97
Autor:
Taisuke Onishi, Hiroki Mikami, Yohei Kishimoto, Hironori Kasahara, Boma A. Adhi, Yuhei Hosokawa, Masayoshi Mase, Keiji Kimura
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783030352240
LCPC
LCPC
Recently multicore technology has enabled development of hundreds or thousands core processor on a single chip. However, on such multicore processor, cache coherence hardware will become very complex, hot and expensive. This paper proposes a parallel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb54c804cbe91ba761abf7ec9dfc8075
https://doi.org/10.1007/978-3-030-35225-7_2
https://doi.org/10.1007/978-3-030-35225-7_2
Autor:
Boma A. Adhi, Keiji Kimura, Yuhei Hosokawa, Hironori Kasahara, Yohei Kishimoto, Masayoshi Mase
Publikováno v:
COMPSAC (1)
A recent development in multicore technology has enabled development of hundreds or thousands core processor. However, on such multicore processor, an efficient hardware cache coherence scheme will become very complex and expensive to develop. This p
Autor:
Akimasa Yoshida, Hironori Kasahara
Publikováno v:
Parallel Computing. 24:579-596
This paper proposes a compilation scheme for data localization using partial-static task assignment for Fortran coarse-grain parallel processing, or macro-dataflow processing, on a multiprocessor system with local memories and centralized shared memo
Autor:
Kenichi Iwata, Hironori Kasahara, Fumio Arakawa, Tohru Nojiri, Kunio Uchiyama, Hideyuki Noda, Idehara Akio, Yasuhiro Tawara, Hiroaki Shikano
Publikováno v:
Heterogeneous Multicore Processor Technologies for Embedded Systems ISBN: 9781461402831
In order to satisfy the high-performance and low-power requirements for advanced embedded systems with greater flexibility, it is necessary to develop parallel processing on chips by taking advantage of the advances being made in semiconductor integr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c362bdef191c74d9617158594009bad
https://doi.org/10.1007/978-1-4614-0284-8_2
https://doi.org/10.1007/978-1-4614-0284-8_2
Autor:
Takamichi Miyamoto, Masayoshi Mase, Hironori Kasahara, Jun Shirako, Hiroki Mikami, Keiji Kimura
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783642133732
LCPC
LCPC
OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de7de28570255d283239b81850e75ad3
https://doi.org/10.1007/978-3-642-13374-9_13
https://doi.org/10.1007/978-3-642-13374-9_13
Publikováno v:
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04).
Chip multiprocessor (CMP) architecture has attracting much attention as a next-generation microprocessor architecture and many kinds of CMP are widely being researched. However, CMP architectures several difficulties for effective use of memory, espe
Autor:
Takamichi Miyamoto, Jun Shirako, Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540280095
LCPC
LCPC
This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 and SGI Altix 3700. The OSCAR compiler hierarchically exploits the coarse grain ta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a178eca7a1e5b736211d28b43e04c4b
https://doi.org/10.1007/11532378_23
https://doi.org/10.1007/11532378_23
Autor:
Hironori Kasahara, Keiji Kimura
Publikováno v:
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650).
With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting important problems However, it has been thought that popular superscalar an
Publikováno v:
Scopus-Elsevier
This paper proposes a parallel processing scheme of electronic circuit simulation using the direct method and evaluates the performance of the scheme on a multiprocessor system named OSCAR (Optimally SCheduled Advanced MultiprocessoR) with centralize