Zobrazeno 1 - 10
of 23
pro vyhledávání: '"WENJIAN YU"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:1467-1480
Autor:
Wenjian Yu, Ming Yang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:4935-4943
A novel technique is proposed to deal with conformal dielectrics for extracting capacitances with floating random walk (FRW) method. It is based on the observation that the transition probabilities for the eight-octant cube exhibit a kind of symmetry
Autor:
Ming Yang, Wenjian Yu
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:946-951
The idea of macromodel was recently proposed for encrypting sensitive structures and accelerating the floating random walk (FRW)-based capacitance extraction. In the existing work, boundary element method (BEM) is employed to generate the macromodel,
Publikováno v:
DATE
In this paper, two techniques are proposed to enhance the floating random walk (FRW) based capacitance solver for handling non-stratified dielectrics in very large-scale integrated (VLSI) circuits. They follow an existing approach which employs appro
Publikováno v:
ASP-DAC
Capacitance extraction and power grid (PG) analysis for IC design involve large-scale numerical simulation problems. As the process technology becomes more complicated and design margin is shrinking, the capacitance field solver and power-grid matrix
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:120-133
The non-Manhattan conductor geometry existing in some capacitance extraction problems brings difficulty to the floating random walk (FRW) method using cubic transition domains. In this paper, techniques are proposed to enhance the FRW method for hand
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34:1977-1990
3-D integrated circuits (3-D ICs) make use of the vertical dimension for smaller footprint, higher speed, lower power consumption, and better timing performance. In 3-D ICs, the inter-tier-via (ITV) is a critical enabling technique because it forms v
Autor:
Taotao Lu, Wenjian Yu
Publikováno v:
ASICON
Designing high-quality flat panel display (FPD) poses a couple of challenges to the electronic design community. To verify the equal signal delay on the wires to pixels and the validity of capacitive touch sensors, the resistance and capacitance of F
Publikováno v:
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields. 29:21-34
Accurately extracting capacitances among the interconnects in modern multi-dielectric technology of integrated circuits is a challenging task. The floating random walk FRW algorithm is advantageous for capacitance extraction and has been extended by