Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Dongyoung Lee"'
Autor:
Moran Zaberchik, Scott Beatty, Sanghuck Jeon, Nir BenDavid, Chanha Park, Sang Ho Lee, Dongsub Choi, Dongyoung Lee, Telly Koffas, Chen Li, Ramkumar Karur-Shanmugam, Dongsoo Kim, Honggoo Lee, Jae Young Park, Hedvi Spielberg, Efi Megged, Dohwa Lee
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
We developed a statistical method that can be applied to overlay metrology tools to improve performance and time-to-results (TTR) of multi-cycle optimization based on the brute force method. First, we evaluated full response surfaces for each combina
Autor:
Seung-Uk Jeong, Sotirios Tsiachris, Jeongwoo Jae, Dongyoung Lee, Chih-Hung Hsieh, Gwang-Gon Kim, Yuna Park, Ji-Hoon Jung, Kyoyeon Cho, Abdalmohsen Elmalk, Chanha Park, Nang-Lyeom Oh, Taekwon Jee, Gratiela Isai, Jungchan Kim, JaeYoung Park, Won-Kwang Ma, Ewa Kasperkiewicz, Rizvi Rahman, Anita Bouma, Sang Ho Lee, WeiTai Lin, Kuo-Feng Pao, Jae-Doug Yoo, Jonggeun Won, Sudharshanan Raghunathan, Hsin-Yu Chen, Kuan-Ming Chen, Sang-Woo Kim, Wolfgang Henke
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay w
Autor:
Chanha Park, Xiaolei Liu, Dongyoung Lee, Chen Dror, Eltsafon Ashwal, Dongsoo Kim, Sanghuck Jeon, Zephyr Liu, Katya Gordon, Honggoo Lee, Eitan Hajaj, Mark Ghinovker, Diana Shaphirov, Sang-Ho Lee, Dongsub Choi, Dohwa Lee, Raviv Yohanan
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
Reduction in on product overlay (OPO) is a key component for high-end, high yield integrated circuit manufacturing. Due to the continually shrinking dimensions of the IC device elements it has become near-impossible to measure overlay on the device i
Autor:
Anna Golotsvan, Efi Megged, Roie Volkivich, Dohwa Lee, Dongsub Choi, Jaesun Woo, Sanghuck Jeon, Jin-Soo Kim, Seongjae Lee, Dongyoung Lee, Honggoo Lee, Chunsoo Kang, Chanha Park, Shlomit Katz
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIV.
As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancemen
Autor:
Jun-Yeob Kim, Dongyoung Lee, Sangjun Han, Aileen Soco, Nang-Lyeom Oh, Chanha Park, Tjitte Nooitgedagt, Dong-Hak Lee, Arno van Leest, Honggoo Lee, Jaap Karssenberg, Mir Shahrjerdy
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIII.
In next generation 3D-NAND devices, accurately determining after-etch overlay for the multi-layer stack is a major challenge. This is especially the case for the multi-tier 3D-NAND structures, where the overlay of the channel holes is an important pe
Autor:
Chanha Park, Minhyung Hong, Sangjun Han, John C. Robinson, Jieun Lee, Tal Marciano, Zephyr Liu, Dana Klein, Dongsub Choi, Roie Volkovich, Ahlin Choi, Hao Mei, Eitan Hajaj, Dohwa Lee, Lilach Saltoun, Jung-Tae Lee, Eitan Herzel, Wayne (Wei) Zhou, Dongyoung Lee, Anna Golotsvan, Jeongpyo Lee, Honggoo Lee, Eran Amit, Sanghuck Jeon, Seongjae Lee
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIII.
Overlay process control is a critical aspect of integrated circuit manufacturing. Advanced DRAM manufacturing overlay error budget approaches the sub-2nm threshold, including all sources of overlay error: litho processing, non-litho processing, metro
Autor:
Roie Volkovich, Eran Amit, Jungtae Lee, Einat Peled, Sangjun Han, Sanghuck Jeon, Minhyung Hong, Jieun Lee, Seungyoung Kim, Seongjae Lee, Tal Yaziv, Honggoo Lee, Dana Klein, Dongsub Choi, Anat Marchelli, Alexander Svizher, Dongyoung Lee, Dohwa Lee, Yuval Lamhot, Aaron Cheng, Ahlin Choi, Eungryong Oh, Jeongpyo Lee, John C. Robinson, Zephyr Liu
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination set
Autor:
Seungyoung Kim, Sangjun Han, Hyowon Park, Minhyung Hong, Sanghuck Jeon, Stilian Ivanov Pandev, Waley Liang, Ahlin Choi, Jieun Lee, Dongyoung Lee, Jeongpyo Lee, Eungryong Oh, Nakyoon Kim, John C. Robinson, Honggoo Lee, Dongsub Choi
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after l
Autor:
Minhyung Hong, Jieun Lee, Guy Ben-Dov, Young-Sik Kim, Eitan Hajaj, Seungyoung Kim, Yoonshik Kang, Dana Klein, Anna Golotsvan, Dongyoung Lee, Ahlin Choi, Saltoun Lilach, Eungryong Oh, Tal Marciano, Dan Serero, Kyuchan Shim, Sangjoon Han, Aharon Sharon, Honggoo Lee
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
As semiconductor manufacturing technology progresses and the dimensions of integrated circuit elements shrink, overlay budget is accordingly being reduced. Overlay budget closely approaches the scale of measurement inaccuracies due to both optical im
Autor:
Irina Brinster, Dongyoung Lee, Dongsub Choi, Honggoo Lee, Jaeson Woo, Hoyoung Heo, Chang-Rock Song, Sangjun Han, John C. Robinson
Publikováno v:
SPIE Proceedings.
Overlay control based on DI metrology of optical targets has been the primary basis for run-to-run process control for many years. In previous work we described a scenario where optical overlay metrology is performed on metrology targets on a high fr