Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Martin Margala"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1411-1418
The continued push to smaller geometries, higher frequencies, and larger chip sizes rapidly resulted in an incompatibility between interconnect needs and projected interconnect performance. As stated in the 2003 International Technology Roadmap for S
Publikováno v:
IEEE Transactions on Reliability. 54:441-448
An efficient defect-oriented parametric test method for analog & mixed-signal integrated circuits based on neural network classification of a selected circuit's parameter using wavelet decomposition preprocessing is proposed in this paper. The neural
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:169-180
A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no pro
Autor:
Martin Margala, Hongfan Wang
Publikováno v:
Integration. 38:185-203
This paper presents a new approach to design for reusability in System-on-Chip applications. The fundamental principle of the new concept is in merging multiple configurations into a single functional architecture that is then represented by a soft r
Publikováno v:
Journal of Electronic Testing. 20:25-37
This paper presents a new approach for detecting defects in analog integrated circuits using the feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting catastrophi
Autor:
Martin Margala, Nelson G. Durdle
Publikováno v:
Microelectronics Journal. 30:193-197
This paper presents a new low-voltage power-efficient adder design, based on a Bipolar Double Pass-Transistor Logic (BiDPL), suitable for VLSI applications. The new adder delivers significantly higher performance for the same amount of power needed t
Publikováno v:
SoCC
In this work, power minimization method for Varicap Threshold Logic (VcTL) implementations is proposed. In this aspect, characteristics of NMOS and PMOS capacitances are investigated. AND-OR gates and full adder (FA) are selected to prove the propose
Autor:
M.S. Dragic, Martin Margala
Publikováno v:
DFT
The feasibility of a non-specification based method for testing of analog integrated circuits in a 0.13 /spl mu/m CMOS process has been explored. The method is an extension of digital I/sub DD/ test to analog circuits. We investigated detection rate
Publikováno v:
DFT
A new parametric approach for detecting defects in analog integrated circuits using the feed forward neural network trained by back-propagation method is presented. The neural network is used for classification of tested circuits by sensing differenc
Publikováno v:
Scopus-Elsevier
European Test Symposium
European Test Symposium
When moving into the billion-transistor era, the direct or bus interconnects in conventional SoC test control models are rather restricted in not only system performance, but also signal integrity and transmission with continued scaling of the featur
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