Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Soo-young Oh"'
Autor:
R. Divecha, B.E. Stine, C.R. Harwoo, O.S. Nakagawa, Dennis Ouma, Duane S. Boning, D. L. Hetherington, J.E. Chung, Soo-Young Oh
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 11:129-140
Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. I
Autor:
Keh-Jeng Chang, Soo-Young Oh
Publikováno v:
IEEE Circuits and Devices Magazine. 11:16-21
Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be pract
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 39:779-789
The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics ar
Publikováno v:
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
As scaling has continued for more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 /spl mu/m as proposed in the SIA Technical Road map. With scaling, device perf
Publikováno v:
1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387).
As scaling is continued down to deep submicron, interconnects become dominating the performance, signal integrity, and reliability of IC chips. However, due to the short history, not much work has been done on the overall interconnect modeling, espec
Publikováno v:
1992 Symposium on VLSI Technology Digest of Technical Papers.
A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect model
Publikováno v:
ICCD
A batch-oriented interconnect modeling system, IPDA (Interconnect Performance Design Assistant), developed for interconnect modeling and design in high-speed VLSI/ULSI systems, is presented. Intrachip communication is degraded by RC delay and crossta
Publikováno v:
ICCD
In this paper we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also describe
Publikováno v:
1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.
This paper presents a new paradigm for fast and accurate 2-D and 3-D interconnect capacitance extraction suitable for sub-micron, multi-level (SMML) conductor systems. According to SMML interconnect process measurements and simulations, there are lin
Publikováno v:
1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.
The trend of the performance degradation, noise and reliability issues and their potential solutions are analyzed for submicron ULSI interconnect lines. The analysis shows that a copper (Cu) line will improve electromigration, but not the interconnec