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pro vyhledávání: '"Philipp Schonle"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1254-1264
This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), whic
Publikováno v:
VLSI Circuits
This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, fi
Publikováno v:
IEEE Journal of Solid-State Circuits, 53 (7)
We report VivoSoC , a system-on-chip realized in 130-nm CMOS for miniaturized medical instrumentation as used in mobile health devices or implantable telemetry systems for animal experiments. It features six neural stimulation channels and acquisitio
Autor:
Thomas Burger, Q. Wang, Luca Benini, Qiuting Huang, Jonathan Bosser, Xu Han, Florian Glaser, Schekeb Fateh, Noe Brun, Philipp Schonle, Giovanni Rovere
Publikováno v:
ESSCIRC
We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation channels and acquisition circuits for 9Ã electrode-based recordings (ExG), 4Ã/32Ã photo-p
In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approxim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2f5a02c31fef509c4de50fb575a9f67
http://hdl.handle.net/11585/544978
http://hdl.handle.net/11585/544978