Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Chih-Wei Liu"'
Publikováno v:
Integration. 48:230-238
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital heari
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 42:127-138
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must ha
Publikováno v:
VLSI-DAT
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we prop
Publikováno v:
ISCAS
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerat
Publikováno v:
EURASIP Journal on Advances in Signal Processing, Vol 2011 (2011)
The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and qu
Autor:
Chih-Wei Liu, Ming-Hung Chang, Tay-Jyi Lin, Siang-Sen Deng, Wei Hwang, Hao-I Yang, Shih-Hao Ou
Publikováno v:
2007 IEEE International Workshop on Memory Technology, Design and Testing.
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low volt
Publikováno v:
SiPS
An n-bit fixed-width multiplier keeps the input-width and output-width the same by truncating the n least significant output bits. In order to reduce the complexity, direct-truncation multipliers omit the half of the partial products corresponding to
Publikováno v:
ISCAS
This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13/spl mu/m implementation. Besides, the complexity-aware co
Publikováno v:
ISCAS (2)
This paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is f
Autor:
Chen-Chia Lee, Tay-Jyi Lin, Chein-Wei Jen, Chie-Min Chao, Chih-Wei Liu, Li-Chun Lin, Shin-Kai Chen, Pi-Chen Hsiao, Chia-Hsien Liu
Publikováno v:
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..
This work presents a DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the d