Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Weichen Liu"'
Autor:
Lei Guo, Sun Wei, Pengxing Guo, Luan H. K. Duong, Hainan Bao, Weigang Hou, Weichen Liu, Chuang Liu
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 31:547-564
The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core interconnection architecture in recent years. However, the traditional electrical lines have very limited bandwidth and high energy consumption, making the photonic inter
Publikováno v:
IEEE Transactions on Computers. 68:1174-1189
Spin-Torque Transfer Magnetic RAM (STT-RAM), one of the emerging nonvolatile memory (NVM) technologies explored as the replacement for SRAM memory architectures, is particularly promising due to the fast access speed, high integration density, and ze
Publikováno v:
IEEE Transactions on Computers. 67:1818-1834
Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent core
FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 28:1905-1918
Dark silicon refers to the phenomenon that a fraction of a many-core chip has to become “dark” or “dim” in order to guarantee the system to be kept in a safe temperature range and allowable power budget. Techniques have been developed to sele
Publikováno v:
Future Generation Computer Systems. 68:234-247
In dark silicon many-core systems, system-level techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the allowable power budget and eliminate thermal hotspot. However, this will unexpectedly incre
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:3027-3040
Network-on-chip (NoC) is promising for the communication paradigm of the next-generation multiprocessor system-on-chip (MPSoC). As communication has become an integral part of on-chip computing, and even the performance bottleneck, researchers are pa
Publikováno v:
ICPADS
In the past few years, the extinction of Moore's Law makes people reconsider the solutions for dealing with the low computing resource utilization of applications on multicore processor systems. However, making good use of computing resources in mult
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6a5a51fca760989b3aaba0f386cc9df6
https://hdl.handle.net/10356/144759
https://hdl.handle.net/10356/144759
Publikováno v:
ICPADS
Heterogeneous Multi-Core Mobile Systems has been widely used to improve performance. However, it faces with the challenge of tradeoff between energy saving and user experience. ARM big. LITTLE architecture, a heterogeneous computing architecture, is
Publikováno v:
2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
Optical network-on-chip (ONoC) architecture offers excellent communication performance for unconflicted messages. However, extra communication delays and energy overheads will be incurred by communication contention, significantly diminishing the ben
Publikováno v:
Journal of Systems Architecture. 100:101661
The standby-sparing (SS) is a promising technique which deploys the dual-processor platform, i.e., one primary processor and one spare processor, to achieve fault tolerance for real-time systems. In the existing SS framework, all applications have th