Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Haroon Ahmed"'
Autor:
David A. Williams, William I. Milne, L. A. W. Robinson, Seung-Beck Lee, Kbk Teo, Gehan A. J. Amaratunga, David G. Hasko, Manishkumar Chhowalla, Haroon Ahmed
Publikováno v:
Microelectronic Engineering. :615-622
We report on a study into electrode fabrication for the gate control of carbon nanotubes partially suspended above an oxidised silicon substrate. A fabrication technique has been developed that allows self-aligned side-gate electrodes to be placed wi
Autor:
O. Groening, V. Semet, Didier Pribat, William I. Milne, Gehan A. J. Amaratunga, G. Pirio, Kenneth B. K. Teo, Vu Thien Binh, A. Loiseau, M. Castignolles, Pierre Legagneux, J. P. Schnell, Haroon Ahmed, Seung-Beck Lee, David G. Hasko, Manishkumar Chhowalla, L. Gangloff
Publikováno v:
Diamond and Related Materials. 12:422-428
Plasma enhanced chemical vapour deposition (PECVD) is a controlled technique for the production of vertically aligned multiwall carbon nanotubes for field emission applications. In this paper, we investigate the electrical properties of individual ca
Autor:
Seung-Beck Lee, David G. Hasko, L. A. W. Robinson, Gehan A. J. Amaratunga, Haroon Ahmed, Kenneth B. K. Teo, William I. Milne, Manish Chhowalla, David A. Williams
Publikováno v:
Nanotechnology. 14:290-293
We have fabricated self-aligned, side-gated suspended multi-walled carbon nanotubes (MWCNTs), with nanotube-to-gate spacing of less than 10 nm. Evaporated metal forms an island on a suspended MWCNT, the island and the nanotube act as a mask shielding
Autor:
Manishkumar Chhowalla, Kbk Teo, Gehan A. J. Amaratunga, V. Semet, A. Loiseau, William I. Milne, Shinbuhm Lee, Pierre Legagneux, Haroon Ahmed, G. Pirio, David G. Hasko, M. Castignolles, O. Groening, Didier Pribat, Vu Thien Binh
Publikováno v:
Nanotechnology. 14:204-211
The ability to grow carbon nanotubes/nanofibres (CNs) with a high degree of uniformity is desirable in many applications. In this paper, the structural uniformity of CNs produced by plasma enhanced chemical vapour deposition is evaluated for field em
Publikováno v:
Nanotechnology. 14:188-191
We describe the fabrication and digital logic operation of superconducting nanotransistors. The nanotransistor is a superconducting weak-link device that has integrated hot-phonon injector heaters to control its switching critical current. The fabric
Autor:
Kenneth B. K. Teo, Haroon Ahmed, Aun Shih Teh, Seung-Beck Lee, Manish Chhowalla, David G. Hasko, William I. Milne, Gehan A. J. Amaratunga
Publikováno v:
Nanotechnology. 14:192-195
We report on the fabrication and field emission of carbon nanotube lateral field emitters. Due to its high aspect ratio and mechanical strength, we use vertically aligned multi-wall carbon nanotubes prepared by plasma-enhanced chemical vapour deposit
Publikováno v:
Microelectronic Engineering. :1063-1067
Procedures have been established for layout reconstruction of complete integrated circuits so that topology and function can be determined. Circuits are imaged repeatedly, after the removal of successive layers, by electron-beam and light-optical tec
Publikováno v:
Microelectronic Engineering. :981-987
We describe the fabrication and operation of a NOR logic gate based on a single, dual-heater superconducting nanotransistor. The nanotransistor is a weak-link device that uses integrated heaters to control its critical current. The fabrication proces
Autor:
Hiroshi Mizuta, G. Evans, Kazuo Nakazato, Haroon Ahmed, Shuhei Amakawa, Andrew C. Irvine, Zahid A. K. Durrani, Kazuhito Tsukagoshi, Heinz Olaf Müller, David A. Williams
Publikováno v:
Nanotechnology. 12:155-159
This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semico
Publikováno v:
Microelectronic Engineering. 53:641-644
Electron-beam techniques and sample-preparation methods have been established to meet the requirements for imaging of complete integrated circuits to determine the layout of each layer in the circuit and the layer-to-layer interconnections. Selective