Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Qiuting Huang"'
Publikováno v:
CICC
We report a photo-plethysmography ASIC realised in a 130nm CMOS technology, which supports multi-channel probe configurations with up to 32 LEDs and 4 photodiodes. The receiver can cover a wide range of (full-scale) input signal strengths between 13n
Autor:
Qiuting Huang, P. Balmelli
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:2161-2169
The design of a fifth-order 4-b quantizer single-loop /spl Sigma//spl Delta/ modulator is presented that achieves 25-MS/s conversion rate with 84 dB of dynamic range and 82 dB of signal-to-noise ratio. Implemented in a 0.18-/spl mu/m CMOS technology,
Publikováno v:
Scopus-Elsevier
A digital-to-analog converter (DAC) composed of a cascaded digital /spl Sigma//spl Delta/ modulator and the combination of a semidigital/digital finite-impulse response (FIR) and an infinite-impulse response (IIR)-SC/RC filter is described. The archi
Publikováno v:
2006 Proceedings of the 32nd European Solid-State Circuits Conference.
This paper describes the implementation of a 10-bit ENOB 50-MS/s CMOS pipeline analogue-to-digital converter (ADC) in a 130-nm process with a supply voltage of 1.2 volts and on-chip voltage buffers. The pipeline stages are scaled in current and area
Autor:
Qiuting Huang, Pio Balmelli
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
The design of a fifth-order 4-b quantizer single-loop ΣΔ modulator is presented that achieves 25-MS/s conversion rate with 84 dB of dynamic range and 82 dB of signal-to-noise ratio. Implemented in a 0.18-μm CMOS technology, the 0.95-mm 2 chip has
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
The IC consists of a 5th-order single-loop tri-level /spl Sigma//spl Delta/ modulator and a multistage digital filter. Measured dynamic range is 86dB over 1 MHz bandwidth. With 79dB peak SNDR, the chip consumes 33mW and occupies 1.5mm/sup 2/.
Autor:
Qiuting Huang, Thomas Burger
Publikováno v:
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
A 3V, 2.8 mW /spl Delta//spl Sigma/-modulator for mobile radio applications has been implemented in a 0.5 /spl mu/m CMOS technology. The circuit has a dynamic range of 86 dB for a 100 kHz input signal bandwidth and achieves a maximum signal to noise
Publikováno v:
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
A 5/sup th/-order single-loop /spl Sigma/-/spl Delta/ modulator has been implemented in a 0.25 /spl mu/m digital CMOS process, where the supply voltage is only 2.5 V and the capacitor option is not available. A tri-level quantizer is used to improve