Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Chih-Wei Liu"'
Publikováno v:
ISCAS
The development of radar technology has always been a hot issue. In recent years, due to the popularization of Advanced Driver Assistance Systems (ADAS), such as autonomous driving system and collision avoidance system, the requirements for radar tec
Publikováno v:
APCCAS
The evolution of wireless communication protocols drives the quest of power-efficient and flexible computing for embedded DSPs, but popular architectures, very-long-instruction-word (VLIW) and application-specific instruction set processor (ASIP), se
Publikováno v:
Journal of Signal Processing Systems. 51:209-223
This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 42:127-138
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must ha
Publikováno v:
ISCAS
Recently, many embedded systems adopt the heterogeneous multi-core processors, such as the TI OMAP and the IBM Cell BE, to allow offloading computation-intensive tasks from the MPU to the DSP for satisfying the increasing complexity of the emerging D
Publikováno v:
2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control.
Underwater acoustic communication systems need Doppler compensation for the server Doppler effects. OFDM (Orthogonal Frequency Division Multiplexing) is widely applied in the underwater acoustic communication systems. FFT is the most computational ke
Publikováno v:
ISCAS
A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modern processors issue multiple instructions simultaneously (i.e. superscalar or VLIW
Publikováno v:
ISCAS
This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the propo
Publikováno v:
ASP-DAC
The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently. However, they suffer high complexity or huge code sizes. In t
Publikováno v:
ISCAS
This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13/spl mu/m implementation. Besides, the complexity-aware co