Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Tadahiro Ohmi"'
Autor:
Tadahiro Ohmi, Tadashi Shibata
Publikováno v:
Journal of Robotics and Mechatronics. 8:508-515
The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic c
Publikováno v:
IEEE Transactions on Electron Devices. 42(1):135-143
A new synapse memory cell employing floating-gate EEPROM technology has been developed which is characterized by an excellent weight-updating linearity under the constant-pulse programming. Such a feature has been realized for the first time by emplo
Autor:
Tadahiro Ohmi, Tadashi Shibata
Publikováno v:
IEEE Transactions on Electron Devices. 40:570-576
Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design e
Autor:
Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Naoto Miyamoto, Yaoko Nakagawa, Tadahiro Ohmi
Publikováno v:
3DIC
This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over t
Autor:
Naoto Miyamoto, Tadahiro Ohmi
Publikováno v:
FPT
For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context., and the MC-FPGA sequentially executes all the contexts one by one. So, the total
Publikováno v:
ASP-DAC
This paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to re
Autor:
Roel Firmeza Pantonial, Naoto Miyamoto, Shigetoshi Sugawa, Koji Kotani, Md. Ashfaquzzaman Khan, Tadahiro Ohmi
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
To implement a user circuit on a Dynamically Reconflgurable FPGA (DRFPGA) the circuit needs to be temporally partitioned into several sub-circuits such that their sequential execution on the DRFPGA yields the same result as that of the user circuit.
Publikováno v:
FPT
This work introduces a new approach to realize timesharing of flip-flops in time-multiplexed FPGAs. In order to implement large circuits in time-multiplexed FPGAs, it is important that flip-flops, as well as combinational logics, must be time-shared
Publikováno v:
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
A minimum-distance-vector fully-parallel-search hardware has been developed based on neuron-MOS (/spl nu/MOS) technology for use in real-time event recognition system. The distance calculation as well as the minimum distance search are conducted base
Publikováno v:
Proceedings of Fifth International Conference on Microelectronics for Neural Networks.
Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in