Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Chih-Wei Liu"'
Autor:
Chih-Wei Liu, Le-Ren Chang-Chien
Publikováno v:
ISCAS
Nowadays the integrated circuit is usually in need of various voltage supports. To efficiently manage the power demand, numbers of power modules are integrated together to form a power management unit (PMU). Since each power module has its own spec,
Publikováno v:
VLSI-DAT
In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoc
Publikováno v:
Integration. 48:230-238
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital heari
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 42:127-138
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must ha
Publikováno v:
VLSI-DAT
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we prop
Publikováno v:
ISCAS
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerat
Publikováno v:
ISCAS
Conventional timing-optimized synchronous circuit is designed and constrained by the longest critical path delay, i.e. the worst-case design. However, the path delay of the circuit is absolutely data-dependent. In the example of an 8-bit multiplier s
Publikováno v:
ISCAS
This paper describes a complexity-effective design of auditory compensation, which is the most important building block in digital hearing aids. A multi-rate architecture and the filter bank design thereof are proposed to significantly reduce the dat
Publikováno v:
ISCAS
A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modern processors issue multiple instructions simultaneously (i.e. superscalar or VLIW
Publikováno v:
ISCAS
This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13/spl mu/m implementation. Besides, the complexity-aware co