Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Chih-Wei Liu"'
Autor:
Le-Ren Chang-Chien, Chih-Wei Liu
Publikováno v:
IEEE Transactions on Industrial Electronics. 68:2437-2446
Power management unit (PMU) is commonly used to manage power modules to achieve high efficient performance for integrated circuits. Inside the PMU, controllers that belong to different power modules could be pretty much similar. If the discrete featu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 66:878-882
For characteristic analysis of the 24 KHz audio, the 10-ms, 18-band quasi-ANSI filter bank has been proposed and designed for advanced hearing aids. To greatly reduce the computation complexity, several time-domain multirate signal processing techniq
Publikováno v:
VLSI-DAT
In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoc
Publikováno v:
VLSI-DAT
Radar technology and its developments have been important issues for decades. With the growth of semiconductor processing technology, the development of circuit design related to THz technology has gradually been noted such as imaging radar system. H
Publikováno v:
VLSI-DAT
We use FFT-based convolution in frequency domain to reduce computational complexity in CNNs. The properties of conjugate symmetry and down-sampling is adopted to further reduce complexity. By eliminating filter weights in CNNs that can save computati
Publikováno v:
Integration. 48:230-238
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital heari
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 42:127-138
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must ha
Publikováno v:
ISCAS
Conventional timing-optimized synchronous circuit is designed and constrained by the longest critical path delay, i.e. the worst-case design. However, the path delay of the circuit is absolutely data-dependent. In the example of an 8-bit multiplier s
Publikováno v:
2008 International Conference on Signals and Electronic Systems.
This paper presents a low-power filter bank design for digital hearing aids, which is compliant with the ANSI S1.11 standard. A multi-rate filtering algorithm and its coefficient design method are proposed, which reduce 94% multiplications. The power
Autor:
Chih-Wei Liu, Ming-Hung Chang, Tay-Jyi Lin, Siang-Sen Deng, Wei Hwang, Hao-I Yang, Shih-Hao Ou
Publikováno v:
2007 IEEE International Workshop on Memory Technology, Design and Testing.
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low volt