Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Tadahiro Ohmi"'
Autor:
Hisaya Sugita, Tetsuya Goto, Shigetoshi Sugawa, Tadahiro Ohmi, Satoru Yamashita, Tomoyuki Suwa, Hidekazu Ishii, Yasumasa Koda, Akinobu Teramoto, Rihito Kuroda
Publikováno v:
ECS Transactions. 66:305-314
Introduction On-chip capacitors are used for various purposes in electronic devices, for example, AC coupling capacitors, bypass capacitors, sample and hold circuits for analog signals, and so on. For these purposes, a high capacitance density is req
Autor:
Shigetoshi Sugawa, Hidetoshi Utsumi, Yasuyuki Shirai, Keiichi Hashimoto, Takatoshi Matsuo, Tadahiro Ohmi, Rihito Kuroda, Akinobu Teramoto, Yukihisa Nakao
Publikováno v:
ECS Transactions. 61:29-37
The SiNx gate spacer formation is one of the key processes in the miniaturized MISFETs, because the thickness of the gate spacer and the Si recess after the gate spacer formation etching have large impacts on the electrical properties of MISFETs [1,2
Autor:
Kazuhide Hasebe, Hirokazu Ueda, Takehiko Nomura, Tadahiro Ohmi, Y. Morozumi, Shigetoshi Sugawa, Hiroshi Kambayashi, Katsushige Harada, Nariaki Ikeda, Akinobu Teramoto
Publikováno v:
ECS Transactions. 58:155-166
The enhancement mode AlGaN/GaN hybrid MOS-HFETs on Si substrates have been demonstrated. The breakdown voltage of over 1.71 kV was achieved by investigating the epitaxial structure. Furthermore, a high integrity SiO2/Al2O3 gate stack has been demonst
Autor:
Tomoyuki Suwa, Tadahiro Ohmi, Rihito Kuroda, Akinobu Teramoto, Tadashi Watanabe, Shigetoshi Sugawa, Yukihisa Nakao
Publikováno v:
ECS Transactions. 45:421-428
High chemical etching resistance is strongly required for silicon nitride at low temperature such as 400oC or below in order to apply to the gate spacer, the contact etching stop layer, because various new materials which are thermally instable are i
Publikováno v:
ECS Transactions. 41:147-156
The atomically flat surface is obtained by the ultra-pure argon ambient at relatively low temperature less than 900 °C, and it can be maintained by using the N2 ambient with light shielding cleaning and the radical oxidation. The crystal originated
Autor:
Tadahiro Ohmi, Akinobu Teramoto, Shigetoshi Sugawa, Kazumasa Kawase, Yukihisa Nakao, Rihito Kuroda, Hiroaki Tanaka, Tomoyuki Suwa
Publikováno v:
ECS Transactions. 41:365-373
The electrical and physical properties of ErSix on n-type Si(100) and Si(551) surfaces are reported. The Schottky barrier heights (SBHs) depend on the Si substrate orientation. On a Si(100) surface, a low electron SBH around 0.3 eV is obtained and th
Pr3Si6N11/Si3N4 Stacked High-k Gate Dielectrics with High Quality Ultrathin Si3N4 Interfacial Layers
Publikováno v:
ECS Transactions. 35:275-284
In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any
Publikováno v:
ECS Transactions. 28:299-309
We demonstrate a low temperature flattening method for the 200-mm-diameter (100) orientation silicon wafers. By annealing in ultra pure argon ambient at 850ºC or above, atomically flat surfaces composed of atomic terraces and steps appear uniformly
Publikováno v:
ECS Transactions. 25:115-129
Introduction It is very important to improve the CMOS performance such as current drivability to satisfy the severer demand of circuits. It was reported that the mobility in the MOSFETs fabricated on flattened Si surface has been improved [1]. On the
Publikováno v:
ECS Transactions. 16:183-192
Microcrystalline Si1-xGex (x~0.8) films have been deposited by RF magnetron sputtering with source frequency of 100MHz. Crystallinity of deposited films has been evaluated by spectroscopic ellipsometry. Detailed investigation on the deposition behavi