Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Shiguo Liu"'
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
Prediction and reduction of substrate warpage is very important to enhance assembly yield, and to improve reliability in the microelectronic packaging industry. Modeling the copper trace pattern of a packaging substrate is a difficult and time consum
Publikováno v:
2011 16th International Solid-State Sensors, Actuators and Microsystems Conference.
We have developed a highly sensitive electric-field sensor with novel comb-shaped microelectrodes. The sensor is based on modulating an incident field with a grounded shutter and measuring the induced charge of sensing electrodes. Owing to the shutte
Publikováno v:
2011 IEEE 24th International Conference on Micro Electro Mechanical Systems.
The paper presented a novel MEMS (Microelectro-mechanicalsystems) electric field sensor (EFS) based on SOI (Silicon on Insulator) fabrication process for detecting internal defect of non-ceramic (composite) insulators. The ability to measure both AC
Autor:
Xianghua Xiao, Aditya Kumar, Gaurav Sharma, Teck Guan Lim, Shiguo Liu, Nandar Su, Ying Ying Lim, Jinchang Zhou, John H. Lau, Phyo Phyo Thaw, Kripesh Vaidyanathan, Srinivasa Rao Vempati
Publikováno v:
2009 59th Electronic Components and Technology Conference.
With the increasing demand for system integration to cater for continuously increasing I/Os as well as higher operating frequencies, EMWLP is emerging as a promising technology for integration. This platform allows integrated passives to be designed
Autor:
John H. Lau, V. Kripesh, Yue Ying Ong, John Doricko, Jiangyan Sun, Nagarajan Ranganathan, Damaruganath Pinjala, Shiguo Liu, Xiaowu Zhang, Gongyue Tang, Tai Chong Chai, Eva Wai, C. J. Vath, Ebin Liao, Srinivasa Rao Vempati, C. S. Selvanayagam, Kalyan Biswas, Hongyu Li
Publikováno v:
2009 59th Electronic Components and Technology Conference.
Because of Moore's (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips an
Publikováno v:
2008 10th Electronics Packaging Technology Conference.
This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design,
Publikováno v:
2008 International Conference on Electronic Packaging Technology & High Density Packaging.
Device speed and functionality requirements are quickly forcing the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and silico
Publikováno v:
2007 9th Electronics Packaging Technology Conference.
This work focuses on co-design of the 1st level and 2nd level solder joint reliability analysis of a flip chip package, with large die. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent
Publikováno v:
2006 8th Electronics Packaging Technology Conference.
The low-k materials have intrinsically lower modulus and poorer adhesion compared to the commonly used dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. F
Publikováno v:
2011 16th International Solid-State Sensors, Actuators & Microsystems Conference (TRANSDUCERS); 2011, p1034-1037, 4p