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pro vyhledávání: '"01"'
Autor:
Siegfried Selberherr, Viktor Sverdlov
Publikováno v:
Solid-State Electronics. 159:43-50
Upcoming mass production of energy efficient spin-transfer torque magnetoresistive random access memory will revolutionize microelectronics by introducing non-volatility not only in memory but also in logic. The pressing issue is to boost the sensing
Autor:
Sorin Cristoloveanu, Gerard Ghibaudo, Licinius Benea, Yasuhisa Omura, Shingo Sato, Irina Ionica
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, 159, pp.197-203. ⟨10.1016/j.sse.2019.03.059⟩
Solid-State Electronics, Elsevier, 2019, 159, pp.197-203. ⟨10.1016/j.sse.2019.03.059⟩
This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affectin
Publikováno v:
Solid-State Electronics, Vol. 159, no.September 2019, p. 77-82 (2019)
This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and
Autor:
Andrzej Mazurak, Robert Mroczyński
Publikováno v:
Solid-State Electronics. 159:157-164
Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Com
Analytical modeling of capacitances in tunnel-FETs including the effect of Schottky barrier contacts
Autor:
Francois Lime, Alexander Kloes, Fabian Horst, Mike Schwarz, Atieh Farokhnejad, Benjamin Iniguez
Publikováno v:
Solid-State Electronics. 159:191-196
In this paper, a charge-based analytical model for intrinsic capacitances in tunnel field-effect transistors (TFETs) is presented. The model is derived for a Si Double-Gate (DG) n-TFET whose flexibility is applicable to single-gate or p-type TFETs as
Autor:
Qing-Tai Zhao, Qinghua Han, Paulus Aleksa, Siegfried Mantl, Juergen Schubert, Thomas Carl Ulrich Tromm
Publikováno v:
Solid-State Electronics. 159:71-76
Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon be
Autor:
Piero Olivo, Cristian Zambelli, Eduardo Perez, Christian Wenger, Mamathamba Kalishettyhalli Mahadevaiah
Publikováno v:
Solid-State Electronics. 159:51-56
In this work, the increase on the filament conductivity during the 1st Reset operation, by using the incremental step pulse with verify algorithm, is investigated in HfO2-based 1T1R RRAM devices. A new approach is proposed in order to explain the inc
Autor:
R. Rodriguez, Javier Martin-Martinez, Mireia Bargallo Gonzalez, M. Pedro, Francesca Campabadal, Montserrat Nafria
Publikováno v:
Dipòsit Digital de Documents de la UAB
Universitat Autònoma de Barcelona
Digital.CSIC. Repositorio Institucional del CSIC
instname
Universitat Autònoma de Barcelona
Digital.CSIC. Repositorio Institucional del CSIC
instname
In this work, an automatic and flexible measurement setup, which allows a massive electrical characterization of single RRAM devices with pulsed voltages, is presented. The evaluation of the G-V maps under single-pulse test-schemes is introduced as a
Autor:
Thales Augusto Ribeiro, Antonio Cerdeira, Rodrigo T. Doria, Magali Estrada, Marcelo Antonio Pavanello, Fernando Avila-Herrera
Publikováno v:
Solid-State Electronics. 159:116-122
This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room te
A new method for characterization of gate overlap capacitances and effective channel size in MOSFETs
Publikováno v:
Solid-State Electronics. 159:184-190
Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development