Zobrazeno 1 - 10
of 40
pro vyhledávání: '"01"'
Publikováno v:
Solid-State Electronics, Vol. 159, no.September 2019, p. 77-82 (2019)
This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and
Autor:
Olivier Faynot, Mikael Casse, Gilles Reimbold, Marcelo Antonio Pavanello, Sylvain Barraud, Bruna Cardoso Paz, Maud Vinet
Publikováno v:
Solid-State Electronics. 159:83-89
This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width).
Autor:
Ali A. Rezazadeh, Mohammad A. Alim
Publikováno v:
Solid-State Electronics. 147:13-18
Detailed analysis of device behaviour on the zero-temperature coefficient (ZTC) points for microwave GaAs based high-electron mobility transistor is presented by means of on-wafer measurements over the temperatures between −40 and 150 °C. This zer
Autor:
Yaopeng Zhao, Yunlong He, Chong Wang, Xue-Feng Zheng, Kai Liu, Xiaohua Ma, Wei Mao, Zeyang Huang, Yue Hao, Ang Li
Publikováno v:
Solid-State Electronics. 186:108109
In this paper, enhancement-mode AlGaN/GaN p-type GaN cap layer high electron mobility transistors (p-GaN HEMTs) with Ti/Au gate metal are fabricated and electrically characterized. The post gate annealing (PGA) treatment at 300 °C for 10 min is util
Publikováno v:
Solid-State Electronics. 145:54-57
The two-finger stacked bottom gate and top gate fin indium gallium zinc aluminum oxide thin-film transistors (IGZAO TFTs) were fabricated. Since the bottom induced channel layer and the top induced channel layer were formed in the stacked TFTs using
Publikováno v:
Solid-State Electronics. 145:40-45
We studied how substrate thinning affected the electronic transport characteristics of AlGaN/GaN HEMTs. By thinning their sapphire substrate from 460 µm to 80 µm, we varied the residual stress in these HEMTs. The thinned sample showed decreased dra
Autor:
Andreas Waag, Kristian Frank, Feng Yu, Bernd Witzigmann, Klaas Strempel, Hans Werner Schumacher, Friedhard Römer, Hutomo Suryo Wasisto, Muhammad Fahlesa Fatahilah
Publikováno v:
Solid-State Electronics. 144:73-77
Gallium nitride (GaN) nanowire transistors are analyzed using hydrodynamic simulation. Both p-body and n-body devices are compared in terms of threshold voltage, saturation behavior and transconductance. The calculations are calibrated using experime
Publikováno v:
Solid-State Electronics. 143:62-68
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm an
Publikováno v:
Solid-State Electronics. 142:36-40
Owing to the great influence of surface passivation on DC and RF performance of InP-based HEMTs, the DC and RF performance of InAlAs/InGaAs InP HEMTs were studied before and after passivation, using an ultra-thin 15 nm atomic layer deposition Al2O3 l
Publikováno v:
Solid-State Electronics. 141:1-6
We demonstrate that N2 and O2 plasma treatment followed by rapid thermal annealing leads to surface stoichiometry modification in a AlGaN/GaN high electron mobility transistor. Both the source/drain access and gate regions respond positively improvin