Zobrazeno 1 - 10
of 70
pro vyhledávání: '"01"'
Autor:
Andrzej Mazurak, Robert Mroczyński
Publikováno v:
Solid-State Electronics. 159:157-164
Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Com
Autor:
Thales Augusto Ribeiro, Antonio Cerdeira, Rodrigo T. Doria, Magali Estrada, Marcelo Antonio Pavanello, Fernando Avila-Herrera
Publikováno v:
Solid-State Electronics. 159:116-122
This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room te
A new method for characterization of gate overlap capacitances and effective channel size in MOSFETs
Publikováno v:
Solid-State Electronics. 159:184-190
Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, 159, pp.90-98. ⟨10.1016/j.sse.2019.03.042⟩
Solid-State Electronics, 2019, 159, pp.90-98. ⟨10.1016/j.sse.2019.03.042⟩
Solid-State Electronics, Elsevier, 2019, 159, pp.90-98. ⟨10.1016/j.sse.2019.03.042⟩
Solid-State Electronics, 2019, 159, pp.90-98. ⟨10.1016/j.sse.2019.03.042⟩
GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28 nm node ultra-thin film UTBB FD-SOI high-k metal gate CMOS technology. The anode current and voltage were measured and simulated for a high number of
Autor:
Renan Trevisoli, Michelly de Souza, Rodrigo T. Doria, Marcelo Antonio Pavanello, Sylvain Barraud
Publikováno v:
Solid-State Electronics. 158:37-45
The aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction
Publikováno v:
Solid-State Electronics. 158:16-21
In this paper, a novel temperature distribution measurement method for packaged integrated circuit (IC) chips is proposed, based on field-programmable gate array (FPGA) embedded ring oscillators. A temperature sensing network is established using the
Publikováno v:
Solid-State Electronics. 156:33-40
Feasibility of fabricating plasmonic circuits by complementary metal–oxidesemiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and en
Autor:
Myung-Hyun Baek, Daewoong Kwon, Jinkyu Kang, Byung-Gook Park, Sung-Bok Lee, Woojae Jang, Seung Hyun Kim, Sang-Ho Lee
Publikováno v:
Solid-State Electronics. 152:41-45
In order to verify the effects of polycrystalline Si (poly-Si) body thickness scale-down on read operation in 3D NAND flash memory which has tube type thin body, TCAD simulations and the measurements of fabricated devices are performed. ID-VG charact
Publikováno v:
Solid-State Electronics. 151:6-10
A strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat induced by high current flow
Autor:
Gerard Ghibaudo, G. Pananakakis
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2018, 149, pp.57-61. ⟨10.1016/j.sse.2018.08.011⟩
Solid-State Electronics, Elsevier, 2018, 149, pp.57-61. ⟨10.1016/j.sse.2018.08.011⟩
International audience; New analytical expressions for the subthreshold swing in FDSOI structures operated in both front gate and bottom gate modes are developed. These new equations (9)-(10) provide an accurate description of the subthreshold swing