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Autor:
KUMAR, Mithilesh, MONDAL, Abir J.
Publikováno v:
Radioengineering; Jun2023, Vol. 32 Issue 2, p207-220, 14p
Autor:
M. Kumar, A. J. Mondal
Publikováno v:
Radioengineering, Vol 32, Iss 2, Pp 207-220 (2023)
Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (Pavg) trade-off in each era with power supply voltage (Vdd) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block
Externí odkaz:
https://doaj.org/article/1cc797740473418290eae9894f884189